1. Field of the Invention
The present invention relates to a method for fabricating flash memory devices.
2. Background of the Invention
In general, a representative example of a flash memory device, that is, a non-volatile memory device whose data is not lost even when power is not supplied to the device, includes electrically erasable and programmable read only memory (EEPROM).
EEPROM is an electrically rewritable non-volatile memory device and generally has a structure employing a stacked floating-gate cell.
In recent years, as the level of integration rapidly increases, there is an urgent need for a reduction in size of the conventional floating gate cell. However, the conventional floating gate cell requires a high voltage upon program/erasure and therefore cannot be shrunk past a certain level.
For this reason, extensive research has been done on non-volatile memory devices and various replacements for the conventional floating gate cell have been proposed, such as Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) cells, Ferroelectric Random Access Memory (FeRAM) cells, and Nitride Read Only Memory (NROM).
Of these, the SONOS cell has been perceived by many as the next-generation cell that will replace the stacked floating-gate cell.
A flash memory device of a conventional SONOS structure is described below with reference to FIG. 1.
FIG. 1 is a cross-sectional view of a flash memory device of a conventional SONOS structure.
As shown in FIG. 1, the SONOS device may include a p-type semiconductor substrate 10. A tunnel oxide layer 12, a trap nitride layer 13, a block oxide layer 14, and a gate electrode 15 of a N+ type polysilicon component, may be formed over a specific region of the semiconductor substrate 10.
The tunnel oxide layer 12, the trap nitride layer 13, and the block oxide layer 14 may be stacked to form an oxide/nitride/oxide (ONO) layer.
First and second insulating layer sidewalls 16 and 17 may be formed on both sidewalls of the gate electrode 15. A light doped drain (LDD) region 18 and a source/drain impurity region 19 may be formed in the semiconductor substrate 10 on both sides of the gate electrode 15.
A metal silicide layer 20 may be formed on the surfaces of the gate electrode 15 and the source/drain impurity region 19. An etch-stop layer 21 may be formed on the entire surface of the semiconductor substrate 10 including the metal silicide layer 20. A pre-metal dielectric (PMD) layer 22 may be formed on the etch-stop layer 21.
In the fabrication process of the conventional SONOS device, after the etch-stop layer 21 is formed, the PMD layer 22 may be formed from borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG) and a densification process may be carried out.
The densification process can employ an annealing process under nitrogen atmosphere at a temperature of 600° C. to 900° C. for 10 minutes to 5 hours, or a rapid thermal annealing (RTA) process under nitrogen atmosphere at a temperature of 700° C. to 1000° C. for 10 to 60 seconds.
After the PMD layer 22 is formed, a low-temperature process of 400° C. or less may be performed. A sintering process may be performed under H2/N2 or H2 atmosphere at a temperature of 400° C. to 435° C. anterior or posterior to wire bonding and pad-open processes, so that dangling bonds, shallow traps and/or interface traps existing at the interface of the ONO layer or the interface of the semiconductor substrate and the tunnel oxide layer are terminated by infiltrated hydrogen. Accordingly, the electrical properties of the SONOS device can be stabilized.
As described above, in the fabrication method of the flash memory device, in the case of the ONO deposition process, the block oxide layer 14 is deposited immediately after the tunnel oxide layer 12 and the trap nitride layer 13 are deposited. Thus, numerous dangling bonds, interface states, shallow traps and/or defects exist at the interface of the trap nitride layer 13 and the block oxide layer 14.
This incomplete interface makes the program/erase characteristics of the SONOS device unstable, e.g., reducing a threshold voltage (Vt) window. This makes it impossible to use the device as a memory device. Further, a retention characteristic (that is, a charge retention ability) and a durability characteristic (that is, a read and write ability) are depreciated, lowering reliability of the device.
In the fabrication method of the SONOS device, it is difficult to raise the temperature of the sintering process to 435° C. or more. Accordingly, not only it is difficult to infiltrate hydrogen into the ONO layer of the SONOS device, but also a probability of the infiltrated hydrogen being combined with dangling bonds, shallow traps and/or interface traps is lowered. Consequently, the stabilization of electrical properties of the SONOS device, such as program and erase characteristics, retention ability, and durability, is limited.